A dual precision IEEE floating-point multiplier

We present a design of an IEEE oating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the la-tency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fteen logic levels. A single-precision multiplication can be followed immediately by another multiplication of either single or double-precision. A double-precision multiplication requires one stall cycle, namely, two cycles after issuing a double-precision multiplication, a new multiplication of either precision can be issued. A new algorithm for computing IEEE-compliant rounding is presented, called injection based rounding. Injection based rounding is simple and facilitates using the same rounding circuitry for diierent preci-sions. Hardware cost is reduced by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions.